There are many applications in which it is desirable to include more than one processing unit in a packaged integrated circuit device in order to increase processing power. This is often performed by replicating the same processor unit across the silicon wafer to achieve a fixed number of processors per packaged device. For example, an integrated circuit may include one microprocessor core, two microprocessor cores, three microprocessor cores, etc.
A problem in the prior art is that it is often more expensive than desired to provide customers with choices in the amount of processing power of packaged devices. For example, consider the situation that an integrated circuit may be designed with anywhere between one to six processing units. Conventionally, each design choice would require the generation of a separate electronic design file that is used to fabricate each design choice in a manner consistent with conventional die cutting and packaging techniques. This includes various design rules to safely and reliably cut and package individual die from a wafer. For example, a design having one processing unit per die conventionally requires a first electronic design file to fabricate a die having one processing unit. In order to fabricate a design having six processing units in accordance with conventional design rules, the electronic design file must be modified to fabricate an individual die having six processing units.
Thus, a problem faced in the prior art is that it is more expensive than desired to provide customers with options in regards to the number of processing units per packaged device.